Shift security left: mitigating hardware vulnerabilities during design stage

We know we can simulate side-channel leakage, and we know we can measure side-channel leakage of a chip. Putting the two together, we show the extent to which simulations can be used to predict leakage during development and how simulations can be used to optimize post-silicon parameter tuning.

In this webinar we will discuss how hardware developers can benefit from advanced Pre-Silicon testing that can predict security vulnerabilities during the design stage. This method saves time and budget, helps to avoid costly redevelopments. However, Pre-Silicon approach can also be combined with traditional testing of a physical chip for Side Channel vulnerabilities. With intelligence accumulated at a Pre-Silicon stage, the speed and efficiency of Post-Silicon evaluation can be significantly improved. This, in turn, not only benefits security, but also helps to speed up the certification process.

This is an on-demand webinar, the recording is available for you anytime after registration. Your hosts for this webinar are Jasper van Woudenberg, CTO Riscure North America and Erwin in’ t Veld, Product Manager at Riscure. During a 45 minute presentation they go over the theory of Pre- and Post-Silicon methods and will provide a practical demonstration using Riscure Inspector.

This is the second meeting in a series of webinars dedicated to the Inspector Pre-Silicon. Here you can also access the recording of the first session.