Technical

Escalating Privileges in Linux using Fault Injection

Escalating Privileges in Linux using Fault Injection

Today’s standard embedded device technology is not robust against Fault Injection (FI) attacks such as Voltage Fault Injection (V-FI)
Safety does not equal Security in Automotive

Safety does not equal Security in Automotive

A security assessment of the resilience against fault injection attacks in ASIL-D certified microcontrollers
Secure Application Programming in the presence of Side Channel Attacks

Secure Application Programming in the presence of Side Channel Attacks

This paper introduces a collection of secure programming patterns for security critical devices. These patterns help developers to mitigate the risk of side channel attacks.
Practical steps to evaluate and protect Secure Boot

Practical steps to evaluate and protect Secure Boot

This paper reveals common weaknesses in Secure Boot implementations and proposes practical steps to enhance security of this critical element of an embedded system.
Learn how to keep your Over-The-Air Updates secure?

Learn how to keep your Over-The-Air Updates secure?

A perspective from the analysts at Riscure Security Lab, which was shared during SEMS, Paris on April 30th, 2017 by CEO Marc Witteman.
Controlling PC on ARM using Fault Injection

Controlling PC on ARM using Fault Injection

Fault injection attacks are a powerful technique to influence the intended behavior of embedded systems.
Why is it so hard to make secure chips?

Why is it so hard to make secure chips?

Why is it so hard to make secure chips? from Riscure
Unboxing the White-Box

Unboxing the White-Box

Typical threat modeling applied in cryptography involves a malicious third party attempting to access content. Download the whitepaper.
Fast and Memory-Efficient Key Recovery in Side-Channel Attacks

Fast and Memory-Efficient Key Recovery in Side-Channel Attacks

Side-channel attacks are techniques to attack implementations of cryptographic algorithms by observing its physical parameter. Read more.