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Riscure contributes to DARPA AISS Project

Author: Riscure Team

We’re thrilled to announce our contribution to a Defense Advanced Research Projects Agency’s (DARPA) project in Automatic Implementation of Secure Silicon (AISS). This project brought together an expert team of Galois, PQSecure Technologies, Riscure, and other strategic partners to develop methodologies and solutions for more secure chip design.

The project’s objective is to demonstrate the feasibility of replacing centralized Hardware Security Modules (HSMs) with alternative Security Engines (SEs) that effectively address prevalent security challenges. Additionally, we aim to show that such cryptographic services can be operationally secure by design, preventing both direct and side-channel vulnerabilities. In contrast, typical engineering designs either ignore operational security or cryptographic Intellectual Property (IP) to expedite time-to-market; or rely on ad hoc security design rules of thumb, resulting in vulnerabilities that are only discovered after the IP has moved to production.

The goal of this project is to create a configurable Silicon Security Engine (SE) capability that can be seamlessly integrated into any System-on-Chip (SoC) design before manufacturing. The aim of this project is to develop an SE which offers cryptographic services for on-device functions, enhancing the overall security of the device. The project aims to deliver simulation-tested soft IP implementations of design-time configurable SEs, ensuring minimal gate count and area. In addition, the project intends to provide SEs with practical interfaces for easy access, resilience against various attacks, and real-time provisioning of sensitive data assets like cryptographic keys. The success of the project will be determined by factors such as SE gate count, demonstrated resilience against power side-channel attacks and interface exploitation, and flexibility in SE design configuration.

About the AISS Project team

The project team includes the Advanced Cryptography and the Rigorous Digital Engineering (RDE) teams at Galois, Inc., the pre-silicon side channel analysis team at Riscure, the cryptography IP design team at PQSecure Technologies, and other partners. Galois’ advanced cryptography team brings deep expertise in cryptographic system and protocol security both for Government and commercial solutions. The Galois RDE team has a track record of success in developing tools for automated hardware design and configuration starting from formal system specifications. PQSecure Technologies has demonstrated continuing success in implementing and assuring side channel resilience of core cryptographic services in soft IP core form. Riscure develops tooling for assessment of side-channel resilience in modern hardware, pioneering in pre-silicon, Post-Quantum Cryptography analysis and SCA vulnerabilities.

This document was cleared by DARPA on April 30, 2024.  ** All copies should carry Distribution Statement “A” (Approved for Public Release, Distribution Unlimited).

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