With Riscure Inspector targeting post-silicon hardware testing and Riscure True Code aiming at software, we recognize that there are other stages in the design process that need coverage. In our Pre-Silicon research, we focus on the early stages of Secure Development lifecycle for Hardware. We aim to provide our customers with Fault Injection and Side Channel Analysis vulnerability root causes before tape-out so that they can fix them easily. This pre-silicon development helps you to save time, effort and money.
Fault injection (FI) is an increasingly important attack vector on hardware, and power/EM Side Channel Analysis (SCA) has shown to remain an important attack vector. Little to no (public) work is done on analysis during chip design or software design, because pre-silicon analysis techniques are lacking. In this webinar we’ll demonstrate techniques making it possible to take a hardware design, simulate relevant faults, and simulate power leakage. Building upon this, we show that it is possible to pinpoint (sets of) gates that are the cause of leakage or FI weaknesses, which is key information for designers to start mitigating these attacks.
We’ll demonstrate a case study on the open-source PicoRV32 core: we can find both FI vulnerabilities in the core as well as in the software running on it, and show how some basic countermeasures can reduce the number of FI possibilities. Similarly, for an open-source AES core we show leaky gates can be identified, and propose localized countermeasure strategies. People interested in hardware design and security can learn how pre-silicon security can help reduce future FI vulnerabilities.
To learn more, please join the webinar and hear from our experts: Jasper Van Woudenberg , Principal Security Innovator at Riscure North America and Dennis Vermoen, Principal Security Innovator at Riscure HQ in The Netherlands.
To join the webinar, please fill in the form below. In case you have any questions, please feel free to reach out to us via inforequest@riscure.com.